1. Technical Field
The present invention relates to a gate drive circuit that drives the gate of a voltage controlled switching element.
2. Related Art
In general, as a gate drive circuit that drives the gate of a voltage controlled switching element such as an insulated gate bipolar transistor (hereafter called an IGBT) or MOSFET, a gate resistor Rg is interposed between a gate drive circuit 100 and the gate of a voltage controlled switching element 101, as shown in FIG. 14, and gate drive capability is adjusted, in order to reduce switching noise and avoid element breakage caused by surge voltage when switching.
An example of a configuration of the gate drive circuit 100 incorporating a gate resistor corresponding to the resistor Rg is shown in FIG. 15. The gate drive circuit 100 shown in FIG. 15 has a configuration in which the source of a PMOS field effect transistor M1 is connected to the positive electrode side of a direct current power source 102 via a gate resistor R1, the drain of the PMOS field effect transistor M1 is connected to the drain of an NMOS field effect transistor M2, and the source of the NMOS field effect transistor M2 is connected to the negative electrode side of the direct current power source 102 via a gate resistor R2. Then, a first stage circuit 103 configured of, for example, an amplifier is connected to the gates of the PMOS field effect transistor M1 and the NMOS field effect transistor M2, and a drive signal formed by a pulse signal is input into the first stage circuit 103.
With the gate drive circuit of FIG. 15, noise, surge voltage, or surge current occurs in the output current and output voltage when the gate resistors R1 and R2 are not used, as shown in FIG. 16A, but when using the gate resistors R1 and R2, it is possible to suppress noise and surge voltage occurring in the output current and output voltage, as shown in FIG. 16B.
Then, when applying a voltage controlled switching element to, for example, a power conversion device, two voltage controlled switching elements Q1 and Q2 are connected in series, and the gates of the voltage controlled switching elements Q1 and Q2 are connected to gate drive circuits 100A and 100B respectively via gate resistors Ra and Rb, as shown in FIG. 17, and it is possible to obtain an output from a node N forming a connection point of the voltage controlled switching elements Q1 and Q2 by alternately turning the voltage controlled switching elements Q1 and Q2 on and off.
At this time, as the gate resistors Rg, Ra, and Rb are interposed, as shown in FIGS. 14 and 17, or the resistors R1 and R2 corresponding to the gate resistors Rg, Ra, and Rb are incorporated, as shown in FIG. 15, in the gate drive circuits 100A and 100B that drive the voltage controlled switching elements Q1 and Q2, the gate input impedance of the voltage controlled switching elements Q1 and Q2 increases in a case in which the voltage controlled switching elements Q1 and Q2 are shifted to an off condition, and also in a case in which an off condition is maintained. Because of this, with the configuration of FIG. 17, when the voltage controlled switching element Q2 is put into an off condition with the gate voltage of the voltage controlled switching element Q2 at an L (low) level, and the voltage of the node N rises owing to shifting the voltage controlled switching element Q1 to an on condition, the gate voltage of the voltage controlled switching element Q2 may rise as shown in FIGS. 18A and 18B due to the effect of a parasitic capacitor C shown by the dotted lines in FIG. 17. At this time, as both of the voltage controlled switching elements Q1 and Q2 are in an on condition, there is a danger of causing an increase in current consumption or a breakage of the voltage controlled switching elements Q1 and Q2. Therefore, although it is preferable that the gate resistances of the voltage controlled switching elements Q1 and Q2 are higher while the gate voltage is changing, it is preferable that the gate resistances are lower in a condition in which the gate voltage change is completed. However, with the gate drive circuits having the configurations of FIGS. 14 and 15, it is not possible to adjust the gate resistances in accordance with operating conditions and shift conditions of the voltage controlled switching elements Q1 and Q2.
In order to suppress an occurrence of this kind of surge voltage and surge current, and an occurrence of switching noise, there is proposed a self-arc-extinguishing semiconductor switching element drive circuit wherein, for example, a charge or discharge of the gate capacitance of an IGBT via a first gate resistor is started when the IGBT is turned on (or when the IGBT is turned off) and, when a voltage is generated at an inductor connected between an auxiliary emitter terminal and main emitter terminal of the IGBT, the gate capacitance of the IGBT is charged (or discharged) via a second gate resistor having a resistance value higher than that of the first resistor, alleviating the speed of a rise (or fall) of the current flowing through the IGBT (for example, refer to JP-A-10-32976).
However, in the heretofore known example described in JP-A-10-32976, the first gate resistor is used at the start of switching, after which, the second gate resistor having a resistance value higher than that of the first resistor is used, in order to suppress surge voltage by reducing the IGBT current change rate (di/dt) or (−di/dt) when switching, and to suppress switching noise caused by the voltage change rate (dV/dt) between the main terminals. Because of this, with the heretofore known example, although it is possible to suppress surge voltage, and to suppress switching noise, the first gate resistor (more specifically, a normally-on gate resistor 12 and a normally-off gate resistor 14 of JP-A-10-32976), which has a constant resistance value, is still connected even after the voltage controlled switching element has shifted to an off condition, meaning that, as previously described using FIG. 17, there is an unsolved problem in that, when the voltage controlled switching element Q2 is put into an off condition, the voltage controlled switching element Q1 is shifted to an on condition, and the voltage of the node N rises, there is a danger of causing a malfunction whereby the voltage controlled switching element Q2 changes to an on condition due to the effect of the parasitic capacitor C.